1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a step gate, which can improve the refresh characteristics of the device.
2. Description of the Prior Art
Currently, as the size of a semiconductor device becomes smaller, it is more and more difficult to secure the capacity of a capacitor. Also, as the magnitude of electric field in the junction regions of a transistor becomes larger, it is more and more difficult to secure the refresh characteristics of a cell area. For this reason, a method is used which makes the effective channel length of a transistor long by the use of a three-dimensional cell other than the existing planar cell.
Particularly, a step gate structure was recently proposed which is formed by recessing a portion of both sides of the active region of a substrate and then forming a step gate over the non-recessed edge portion of the active region and the recessed portion of the active region. In this structure, the effective channel length required for the operation of the gate is increased, resulting in an increase in the threshold voltage, leading to an improvement in the refresh characteristics.
FIGS. 1A to 1G are cross-sectional views for explaining each step of a method of manufacturing a semiconductor device having a step gate.
As shown in FIG. 1A, the pad oxide film 11 and the pad nitride film 12 are sequentially deposited on the substrate 10 having an active region and a field region. Then, the pad nitride film 12 is etched so as to expose the field region, and pad oxide film 11 and the silicon substrate 10 are etched using the remaining pad nitride film 12 as an etch barrier, thereby forming the trench 13 in the field region. Then, on the resulting substrate, the gap-fill oxide 14 is formed so as to fill the trench 13.
As shown in FIG. 1B, the gap-fill oxide film is then subjected to chemical mechanical polishing (hereinafter, also referred to as “CMP”) until the pad nitride film is exposed. Next, the remaining pad nitride film is removed to form an isolation film 14a on the field region of the substrate. Then, the cleaning process 15 is performed so as to in order to remove a native oxide film (not shown) present on the substrate 10.
As shown in FIG. 1C, the hard mask oxide film 16 is then formed on the active region of the substrate 10.
As shown in FIG. 1D, the hard mask oxide film 16 is then etched so as to expose both sides of the active region. Then, exposed portion of both sides of the active region is etched using the remaining hard mask oxide film 16, thereby recessing the active regions. At this time, a portion of the isolation film, adjacent to the edge of the active region, is also recessed. The recessed portion of the substrate 10 will be contacted with a capacitor to be formed later.
As shown in FIG. 1E, the remaining hard mask oxide film 16a is then removed. Next, on the active region of the substrate 10, the screen oxide film 17 is formed. Then, although not shown in the drawings, a well ion implantation process and a channel ion implantation process are sequentially performed.
As shown in FIG. 1F, the screen oxide film is then removed. Following this, the gate oxide film 18 is then formed on the surface of the active region of the substrate 10. Next, the doped polycrystalline silicon film 19, the tungsten silicide film 20 and the gate hard mask film 21 are sequentially formed on the entire surface of the substrate 10 including the gate oxide film 18.
As shown in FIG. 1G, the gate hard mask film 21 is then etched in a gate pattern shape. Next, the tungsten silicide film 20, the doped polycrystalline silicon film 19 and the gate oxide film 18 are etched by using the remaining gate hard mask film 21 as an etch barrier, thereby forming a step gate on each of both edges of the central portion of the active region and the recessed portion of the active region, adjacent to each of the edges.
However, in the method of manufacturing the semiconductor device according to the prior art, the step of forming the hard mask oxide film 16 is additionally performed as compared to the existing method of forming a planar cell. This additional step makes the process complex and results in an increase in manufacturing costs.
Also, in the cleaning process conducted to remove the native oxide before the formation of the hard mask oxide film 16, the isolation film 14a will be attacked by etchants, thus causing variations in the channel profile of the isolation film, such as an increase in moat depth and a reduction in effective fox height (FOX). This will result in rapid deterioration in the refresh characteristics of the device.
Furthermore, as the etching process of recessing both sides of the active region of the substrate 10 is progressed, a portion of the edge of the active region of the substrate 10, adjacent to the isolation film 14a, will have a sharp profile. For this reason, when supply voltage (Vcc) required for the operation of the device is applied to the gate 22, an electric field intensive effect will occur which increases the magnitude of electric field at a portion of the substrate having the sharp profile. Thus, the leakage current of the device will be increased, resulting in deterioration in the gate oxide integrity of the device. Also, in the etching process for recessing the active region of the substrate 10, not only the surface of the silicon substrate 10 will be damaged but also the recessed depth of the substrate 10 will become non-uniform, resulting in variations in the channel profile of the device. As a result, the refresh characteristics of the device will be deteriorated.